Generally, in fabrication of an IC device, a photolithography process may be utilized to print/pattern cavities/regions on a surface of a silicon (Si) substrate for creating various devices (e.g., transistors) and circuits to form the IC device. Different cavities may be formed at different stages of the fabrication process. In some instances, the cavities may have different shapes or sizes and may be created in different regions of a substrate. For example, a cavity intended to form a source region for a field-effect transistor (FET) may have a certain size, may be at a certain location in the substrate, or may be filled with a certain material. In another example, channels in a metal layer may be filled with copper (e.g., to interconnect different devices in the IC) or a shallow trench isolation (STI) region may be filled with an oxide. Some cavities may be formed at the same time with the intention that they would substantially have the same size, shape, and extend to the same depth in a substrate. However, some of the cavities may be formed on an area of the substrate that has already gone through a prior process that has affected the surface geometry of that area on the substrate. In such a case, cavities formed on the affected surface may be different than cavities formed on an adjacent surface area.
FIGS. 1A and 1B are cross sectional diagrams of an example IC device. FIG. 1A illustrates an example FINFET IC device 100 that includes substrate 101; a plurality of STI regions 103, 103a, and 103b; a plurality of gate electrodes 105, 105a, 105b, 105c, and 105d placed over corresponding fins formed in the substrate; source/drain cavities 107a, 107b, 107c, and 107d. In this example, the gate electrode 105 is a dummy gate placed over the STI 103 that separates neighboring transistors. As shown, the cavities 107b and 107c adjacent to the sides of the STI 103 extend deeper into the substrate 101 when compared to their respective adjacent cavities 107a and 107d, wherein the depth differences are indicated by markers 109a and 109b. During the IC fabrication, source/drain materials may be epitaxially (epi) grown in the cavities 107a to 107d to respective levels 111a to 111d; however, due to the depth difference in the cavities 107b and 107c, the material levels and surfaces 111b and 111c are irregular and not to the same level (underfilled) as their neighboring cavities 111a and 111d, respectively. The irregular levels and surfaces of the materials in the cavities 107b and 107c can present issues when connecting source/drain contacts to the surfaces 111b and 111c. 
FIG. 1B depicts a step in the current fabrication process in which the silicon around STI region 103 is recessed or gouged to prevent side oxide loss at the SDB during a subsequent fin reveal. The recess 113 lowers the starting surface for forming cavities 107b and 107c, thereby creating the depth differences 109a and 109b. 
A need therefore exists for a methodology enabling creation of uniform source/drain cavities in a substrate of an IC device and the resulting device.